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Computer Architecture past paper
Computer Architecture past paper

Q1:

(a) There is a RAM with the capacity of 8 GByte. The word size is 4 Byte.

Calculate the number of bits required for address if

  • Memory is word addressable
  • Memory is byte addressable.

(b) Describe salient features of Von Neumann architecture.

Q2: Solve it as the instruction is zero address instruction

Y=(A+B*C-DY (E+F G*H+D).

Q3: One computer system with 8 GByte memory and word size is 4 Byte (same in the

Q1). The length of instruction is equal to one word. If this system is word

addressable then what will be the size of below mentioned registers in bits

(a) MAR

(b) MDR

(a) PC

(d) IR

(e) All General purpose registers

Q4:

(a) Differentiate between Direct addressing mode and indirect addressing mode with Examples.

(b) What are the phases for computation of an instruction.

Q5:

(a) what are the 4 signals exchanged between CPU and Main Memory to complete memory access cycle?

(b) If we want to use Indexed register mode and no special purpose register is available as index register; what is the solution and what change is required to make in instruction format.

(c) Format of instruction

(d) Immediate addressing mode




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